The internet of things (IOT) involves billions of mobile devices connected to the cloud with infinite possibilities for data. Each of these devices will require, at a minimum, a microcontroller to add intelligence to the device, one or more sensors to allow for data collection, one or more chips to allow for connectivity and data transmission, and a memory component. Semiconductor device manufacturers are constantly confronted with device integration challenges as consumers want electronics to be smaller, more portable and more multi-functional than ever.
Some traditional system in package (SIP) technologies include embedded die substrates (embedded wafer level package eWLP), die side-by-side wire-bonded SIP's, small outline integrated circuit packages (SOIC), quad flat no-lead packages (QFN), and fan-out type SIP's. Related U.S. patent application Ser. No. 15/718,080 teaches an Embedded Trace Substrate (ETS) System in Package technology integrating Silicon dies and passive components with an ETS substrate as the interconnection between top and bottom sides. It is desired to develop an ultra thin ETS substrate for the thin form factor requirement. Design considerations for the ultra-thin ETS substrate include load-unload, manufacturing process handling, crack risk concern, substrate planarity, and warpage performance.
U.S. Pat. No. 9,565,774 (Lee) and U.S. Patent Applications 2016/0307847 (Lee et al) and 2016/0174381 (Lee et al) disclose methods of forming and using embedded trace substrates (ETS). U.S. Pat. No. 9,711,502 (Huang et al) and U.S. Pat. No. 8,581,405 (Dertinger et al) show components on both sides of a substrate. U.S. Pat. No. 10,049,961 (Qi et al), U.S. Pat. No. 9,601,435 (Kim et al), and U.S. Pat. No. 9,530,714 (Kalchuri et al) describe components embedded in one or more cavities for a thinner package.